Bao Web Development

MIPS CPU Implementation in Verilog

As part of my final in Computer Organization and Assembly Level Programming (Cpr E 381) I described a multicycle MIPS CPU in Verilog. I also synthesized it and tested it by writing a Fibonacci calculator and some other arithmetic programs. The MIPS instruction set was chosen because its versatility and simplicity made it a good model of how to implement a CPU and the associated instruction set. By comparing and contrasting the design of a multicycle to a single cycle and pipelined CPU the project was suppose to give me insight into the design tradeoffs invovled in CPU design.

System Design Considerations

To simplify the design process the CPU was segmented into modules that operated like black boxes. Modules interacted with each other via the data path wires entering and exiting other modules. The modular design process enabled me to have an intuitive high level sense of how the system works. Having intuition as a tool enabled me to identify and exploit spatial and temporal locality amongst modules to optimize performance.

One of the performance optimizations chosen was the multicycle design. The introduction of this optimization increased the complexity of the control circuit that synchronized the flow of data along the data paths. The adoption of a state machine as a method of modeling the control circuit allowed the complexity of the logic to be managed, however, care was taken to keep the physical implementation simple so that spatial overhead did not impede the temporal locality gained from a multicycle implementation. The MIPS instruction set demonstrated the considerations necessary to maximize temporal locality without sacrificing spatial locality. It strived to make the instructions share as many data fields as possible to maximize sharing of the data path, which maximized spatial locality.

Concluding Thoughts

This project was a very great experience because it required me to analyze and document the inner workings of a CPU. It also required me to learn the naunced trade offs in the varying designs such as single cycle, multicycle, or pipelined. It also introduced me to software tools such as the Quartus II IDE that enabled me to describe, synthesize, and debug the CPU.

The full specifications of the project can be viewed here. You can also download the full source in this zip file.